This invention broadly relates to a multiple line buffer type memory LSI (Large Scale Integration) in which a plurality of line buffers are added to the memory section. More specifically, this invention is directed to a multiple line buffer type memory LSI which reduces delays in memory access caused by write-back operation from the line buffer to the memory section.
Recently, a great attention has been paid for the multiple line buffer type memory LSI as a technique for achieving higher performance of memory LSIs.
A multiple line buffer type memory LSI is based on a process comprising the steps of adding a multiple line buffer section having a plurality of line buffers to a memory section within a memory LSI, prefetching (previously reading out data) data stored in a memory section to any of the plurality of line buffers, and upon memory access, causing access to the line buffer.
The multiple line buffer type memory LSI has an object to effectively reduce a delay time occurring upon memory access by providing a high-speed-accessible multiple line buffer section as described above.
A typical example of the above-mentioned multiple line buffer type memory LSI is VCM (Virtual Channel Memory) Architecture announced by NEC Corporation. This VCM Architecture is industrialized as a commercial product by the application of 128-Mbit DRAM (Details have been released by NEC Corporation in the name of 128 Mb VC (Virtual Channel) SDRAM Data Sheet.
FIG. 1 is a block diagram illustrating a typical configuration of a related multiple line buffer type memory LSI, schematically showing the block configuration of 128 Mb VC-SDRAM. The conventional multiple line buffer type memory LSI shown in FIG. 1 will hereinafter be referred to as the related art 1.
As shown in FIG. 1, the related art 1 comprises an address buffer 104, a command decoder 105, a control circuit 106, a memory section 107, a multiple line buffer section 108, and a data buffer 109, and has, as external terminals, an address input terminal group 101, a command input terminal group 102 and a data input/output terminal group 103.
A command indicating operational contents in the multiple line buffer type memory LSI is entered into the command input terminal group 102, and the entered command is decoded by the command decoder 105 and entered into the control circuit 106.
An address specifying a place where data in this multiple line buffer type memory LSI are stored is entered into the address input terminal group 1. The entered address is latched by the address buffer 104 and entered into the control circuit 106.
The control circuit 106 controls the memory section 107, the multiple line buffer section 108 and the data buffer 109 on the basis of the input from the command decoder 105 and the address buffer 104.
The memory section 107 includes a row decoder 110, a memory cell array 111 and a sense amplifying section 112.
The memory cell array 111 is divided into pages, which are data transfer units, between the memory cell array and the sense amplifying section 112.
The row decoder 110 selects a page from those in the memory cell array 111 on the basis of the address entered via the address input terminal group 101. The sense amplifying section 112 activates (amplifies) and retains the page selected by the row decoder 110.
The multiple line buffer section 108 is provided with a line selector 113, a column decoder 114, and one or more line buffers 115. Herein, it is to be noted that the line buffer may be referred to as a channel in the related art 1.
Each line buffer 115 is divided into words which are data transfer units between the line buffer and the data buffer 109.
The row decoder 114 selects a word from those in the line buffer 115 on the basis of the address entered via the address input terminal group 101, and the line selector 113 controls the respective line buffers 115.
In the case of an ordinary DRAM (hereinafter referred to as a xe2x80x9cpage type memory LSIxe2x80x9d), data are read out in units of a word from the activated page which is read out into the sense amplifying section.
Herein, it is noted that a typical example of page type memory LSI is SDRAM, the details of which has been published by NEC Corporation as xe2x80x9c128 Mb SDRAM Data Sheetxe2x80x9d.
By contrast, data for the portion called a segment in an activated page are read and written in a lump with the multiple line buffer section 108 in the case of the VC-SDRAM in the related art 1 shown in FIG. 1.
Memory access in the related art 1 is carried out by two-stage operations comprising background operations and foreground operations.
In this event, the background operations mean operations necessary for data transfer in units of a segment conducted between the memory section 107 and the multiple line buffer section 108.
The foreground operations mean data transfer operations in units of a word performed between the multiple line buffer section 108 and the data input/output terminal group 103.
The background operations mainly comprise the following four operations: a page opening operation (ACT command) for activating the page and reading it out into the sense amplifying section 112; a prefetch operation (PFC command) for reading out a desired segment from the page read out (activated) into the sense amplifying section 112 in the memory section 107 into the multiple line buffer section 108; a restore operation (RST command) for writing back the segment into the page read out (activated) into the sense amplifying section 112 in the memory section 107 (RST command); and a page closing operation (PRE command) for preparing for activation by closing the activated page.
On the other hand, the foreground operations mainly includes the following two operations: a buffer read operation (READ command) for reading out a word from a desired line buffer 115 in the multiple line buffer section 108; and a buffer write operation (WRIT command) for writing words into a desired line buffer 115.
In the related art 1, the multiple line buffer section 108 is full-associatively configured. This means that it is possible to read out a segment at an arbitrary position into an arbitrary line buffer 115.
The following three methods are available for memory access in the related art 1, varying with data retained in the line buffer 115.
FIG. 2 is a timing chart illustrating an example of the data read operation in the multiple line buffer type memory LSI shown in FIG. 1.
1. Hitting case (see FIG. 21A): This represents a memory access method applicable when there are data to be accessed in the line buffer 115, and comprises the step of directly accessing (READ) the line buffer 115 storing the data. In this case, memory access can be performed at a high speed.
2. Error case (see FIG. 2B): A memory access method applicable when data to be accessed are not present in the line buffer 115, but there is an overwritable line buffer (a line buffer retaining the same data as in the memory 107, a line buffer not as yet used). This method comprises the steps of transferring the data to be accessed from the memory section to the overwritable line buffer (ACT-PFC), and then, accessing (READ) the line buffer 115.
3. Write-back case (see FIG. 2(C)): The memory access method applicable when the data to be accessed are not present in the line buffer 115 and there is no overwritable line buffer, comprising the steps of first preparing an overwritable line buffer by writing back the data of the line buffer 115 into the memory section 107 (RST), then, transferring the data to be accessed from the memory section 107 to the line buffer 115 made overwritable (ACT-PFC), and then, accessing the line buffer 115 (READ).
In the related art 1, as described above, the aforementioned write-back case necessitates an operation of writing back the data of the line buffer into the memory section, and this data writing-back operation results in a longer delay time of memory access.
It is therefore an object of this invention to provide a multiple line buffer type memory LSI which is capable of reducing delays in memory access caused by write-back operation of data from the line buffer to the memory section.
To achieve the aforementioned object of the present invention, the invention provides a multiple line buffer type memory LSI having a data input/output terminal group for input/output of data, a memory section in which write and read of data entered or output via the data input/output terminal group are performed, a multiple line buffer section comprising a plurality of line buffers for retaining data previously read out from the memory section, and a control circuit performing control of the apparatus as a whole, in which the line buffers are accessed upon memory access.
The multiple line buffer type memory LSI has one or more write-back buffers retaining copies of the data in the line buffers.
When there is no such line buffer retaining the data read out from the memory section in the multiple line buffer section, the control circuit copies the data retained in any of the line buffers in the multiple line buffer section, causes the write-back buffer to temporarily retain the copies of data, then, causes the line buffer to retain the data read out from the memory section, and writes back the data temporarily retained in the write-back buffer to the memory section.
In an embodiment of the multiple line buffer type memory LSI of the invention, the multiple line buffer type memory LSI has a command input terminal group into which a command for indicating operational contents in the multiple line buffer type memory LSI.
The control circuit can copy the data retained in any of the line buffers in the multiple line buffer section, cause the write-back buffer to temporarily retain the copies of data, and then, cause the line buffer to retain the data read out from the memory section, in response to a command entered into the command input terminal group.
In an embodiment of the multiple line buffer type memory LSI of the invention, the control circuit permits write-back of the data temporarily retained in the write-back buffer into the memory section.
In an embodiment of the multiple line buffer type memory LSI of the invention, the multiple line buffer type memory LSI has a command monitoring circuit which detects as to whether or not the command has been entered into the command input terminal group within a prescribed period of time.
The control circuit automatically writes back the data temporarily retained in the write-back buffer into the memory section in compliance with the result of detection in the command monitoring circuit.
In an embodiment of the multiple line buffer type memory LSI of the invention, the multiple line buffer type memory LSI has an address input terminal group into which an address of indicating a place when the data in the multiple line buffer type memory LSI are stored.
Each of the line buffer and the write-back buffer has an address tag retaining an address specifying the place in the memory from among addresses entered into the address input terminal group.
When causing the data read out from the memory section to be retained in the line buffer, the control circuit writes the address used for the read operation in the address tag of the line buffer. When the data retained in the line buffer are copied and retained temporarily in the write-back buffer, writes the address retained in the address tag of the line buffer into an address tag of the write buffer; and writes back the data temporarily retained in the write-back buffer into the memory section by using the address retained in the address tag of the write-back buffer.
In an embodiment of the multiple line buffer type memory LSI of the invention, the memory section comprises a plurality of banks.
A plurality of the line buffers and the write-back buffers are provided in accordance with the plurality of banks.
In an embodiment of the multiple line buffer type memory LSI of the invention, the write-back buffer may be an FIFO type buffer from which the data are read out in the sequence of write of the data.
The control circuit writes back the data retained in the write-back buffer into the memory section in the sequence in which the data of the line buffer have been retained in the write-back buffer.
In an embodiment of the multiple line buffer type memory LSI of the invention, the multiple line buffer type memory LSI has a data line pair having two wiring lines for connecting the memory section, the line buffer and the write-back buffer to each other.
The memory section, the line buffer and the write-back buffer perform mutual data transfer by means of a micro-potential difference from a certain reference potential of the data line pair.
An embodiment of the multiple line buffer type memory LSI of the invention, further comprises switches for switching over the data line pair between a turn-on state and a turn-off state of the memory section, the line buffer and the write-back buffer, respectively.
Buffer circuits with amplifying function for amplifying the micro-potential difference of the data line pair are arranged in the line buffer and the write-back buffer, respectively.
In the present invention having the above-mentioned configuration, one or more write-back buffers retaining copies of data in the line buffer are provided. When there is no line buffer retaining data read out from the memory section, the data retained in any of the plurality of line buffers are copied and temporarily retained in the write-back buffer.
Data transfer from the line buffer to the write-back buffer can be performed at a high speed as compared with data transfer from the line buffer to the memory section, and data write-back operation can be carried out at any time into the memory section unless the data of the write-back buffer are rewritten. It is therefore possible to temporarily retain copies of data of the line buffer in the write-back buffer, and then immediately execute access to the line buffer. This reduces delays in access caused by data write-back operation.